転職・求人情報の詳細をご覧になる場合は会員登録（無料）が必要です
Senior Digital Design Engineer
年収：800万 ～ 2000万
採用企業案件
SiTime Japan合同会社
-
- 会社規模非公開
- その他
| 部署・役職名 | Senior Digital Design Engineer |
|---|---|
| 職種 | |
| 業種 | |
| 勤務地 | |
| 仕事内容 |
We are hiring a Senior Logic and Digital Circuit Design Engineer. We at SiTime take pride in being the only company in the market that offers MEMS-based timing solutions. Our MEMS dies are uniquely complemented by our CMOS dies in the same package. We use state of the art analog and digital circuits to achieve very aggressive design specs for our all our timing solutions. Our precision timing products keep pushing the boundaries of the industry across all dimensions and are by far superior to our competition. This has enabled us to continuously gain market share. This has been achieved by pushing the innovation boundaries in the areas of MEMS and CMOS.Consisting of analog and digital blocks, our CMOS dies present unique technical challenges. The digital portion of our chips has been growing in the past few years and is expected to grow more rapidly in the upcoming years as our functionality and feature sets scale up. To address our unique technical challenges, we are looking for a strong Senior Digital Design Engineer with a solid background in key digital design and implementation areas. As a Senior Digital Design Engineer, you will be responsible for: ・Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document(PRD) ・Developing the Register Transfer Level(RTL) design from the micro-architecture specification specification using Verilog or SystemVerilog as the HDL ・Developing standalone testbenches to verify the RTL behavior ・Writing and verifying System Verilog Assertions (SVA) for a design ・Writing timing constraints and clock definition for synthesis and place and route tools ・Running industry-standard synthesis tools(e.g.,Genus or Design Compiler) and being able to fix the timing problems if they arise ・Understanding various design tradeoffs including timing/ara/power and knowing how to improve them ・Reading and understanding the Static Timing Analysis (STA) reports from an industry-standard STA tool(e.g., Prime Time) ・Cross functional interactions and communication with various teams within SiTime including analog, verification,backend,system and test engineering teams ・Post-Si bring-up and debugging |
| 応募資格 |
【必須（MUST）】 【Minimum Requirements】・Master’s degree in electrical engineering plus 5 years of relevant work experience in the industry ・Excellent verbal and written communication skills in English ・Proficient in Verilog and System Verilog ・Experience in digital logic design fundamentals such as clock divider circuits,multi-clock logic designs,CDC, FIFO,FSM,etc ・Experience in designing digital logic that interact closely with analog circuits ・Basic understanding of Discrete time Signal Processing theory and FIR and IIR filter design ・Solid experience in dig in digital design flow including RTL design, synthesis, timing constraints, and STA ・Skilled in scripting languages Perl/Tel/Python 【Preferred qualifications】 ・PhD in electrical/computer engineering plus 2-3 years revelant industry experience ・2-5 years experience in designing high-precision digital arithmetic logic and Digital Signal Processing ・2-5 years of experience in designing Digital Phase-Locked Loops(DPLL) ・Experience in complex FSM design ・Familiarity with Matlab, Simulink or any other high-level modeling tools ・Experience in low-power digital design flow ・Basic understanding of the Control Theory |
| アピールポイント | 海外事業 フレックスタイム |
| 受動喫煙対策 | 喫煙室設置 |
| 更新日 | 2024/07/30 |
| 求人番号 | 3726820 |
採用企業情報
- SiTime Japan合同会社
-
- 会社規模非公開
- その他
-
会社概要
【本社所在地】東京都港区港南1丁目8-27
【事業内容】微小電子機械システム（MEMS）及びアナログ半導体の研究及び開発
転職・求人情報の詳細をご覧になる場合は会員登録（無料）が必要です